File1, 2, & 3 for gjohnson:



The primary goal of CISC architecture is to complete a task in as few
lines as possible. This is achieved by building processor hardware that is
capable of understanding and executing a series of operations. For this
particular task, a CISC processor would come prepared with a specific
instruction (we'll call it "MULT:).

When executed, this instruction loads the two values into separate
registers, multiplies the executed, this instruction loads the two values
into separate registers, multiplies the operands in the execution unit,
and then stores the product in the appropriate register. Thus, the entire
task of multiplying two numbers can be completed with one instruction:

MULT is what is known as a "complex instruction". It operates directly on
the computer's memory banks and does not require the programmer to
explicitly call any loading or storing functions. It closely resembles a
command in a higher level language. For instance, if we let "a" represent
the value, then this command is identical to the C statement.


RISC processors only use simple instructions that can be executed within
one clock cycle. Thus, the "MULT" command described above could be divided
into three separate commands: "LOAD," which moves data from the memory
bank to a register, "PROD," which finds the product of two operands
located within the registers, and "STORE," which moves data from a
register to the memory banks.

In order to perform the exact series of steps described in the CISC
approach, a programmer would need to code four lines of assembly.

At first, this may seem like a much less efficient way of completing the
operation. Because there are more lines of code, more RAM is needed to
store the assembly level instructions. The compiler must also perform more
work to convert a high-level language statements into code of this form.


However, the RISC strategy also brings some very important advantages.
Because each instruction requires only one clock cycle to execute, the
entire program will execute in approximately the same amount of time as
the multi-cycle "MULT" command.

These RISC "reduced instructions" require less transistors of hardware
space than the complex instructions, leaving more room for general purpose
registers. Because all of the instructions execute in a uniform amount of
time (i.e. one clock), pipelining is possible.

Separating the "LOAD" and "STORE" instructions actually reduces the
amount of work that the computer must perform. After a CISC-style "MULT"
command is executed, the processor automatically erases the registers. If
one of the operands needs to be used for another computation, the processor
must re-load the data from the memory bank into a register.

No lines are longer than 80 characters, TYVM. Other specified properties aren't being scored automatically at this time so this is not necessarily good news...